The present invention relates to an arrangement for testing field-effect transistors. The present invention more particularly relates to such an arrangement which may be utilized to advantage for testing and locating defective field-effect transistors utilized in the memory cells of random access memory arrays.
Each memory cell of a random access memory generally includes six field-effect transistors. Four of the field-effect transistors, two pull-up field-effect transistors and two pull-down field-effect transistors, form a cross coupled latch well known in the art for maintaining logic ones or zeros in storage. Each cell is associated with a unique combination of a row conductor and a pair of column conductors. Each column conductor is coupled through a pass field-effect transistor to one side of the cross coupled latch. The gates of the pass field-effect transistors are also coupled to the associated row conductors. When a memory cell is accessed, the pass field-effect transistors are rendered conductive by a voltage applied to the pass field-effect transistor gates through the associated row conductor. For a read access, a sense amplifier senses the voltage potential across the associated pair of column conductors. For a write access, suitable voltages are applied to the associated pair of column conductors to set the cross coupled latch to the proper state.
Obviously, all of the memory cells of a memory array must be tested by its manufacturer prior to its shipment and eventual use. This requires the testing of the pull-up and pull-down field-effect transistors of the memory cell cross coupled latches.
Such memory cells have been traditionally tested by writing logical ones into all of the memory cells and then reading each cell to determine if the pull-up field-effect transistor on one side of the latch and the pull-down field-effect transistor on the other side of the latch are functioning properly. Then, a logical zero is written into all of the memory cells and again each cell is read to determine if the opposite combination of pull-up and pull-down field-effect transistors are functioning properly. Each time the memory cell is written into, a wait period is required to allow for any capacitive charge resulting from a defective transistor to dissipate. Otherwise, a pull-up field-effect transistor may appear to be functioning properly when, in fact, it is defective. Locating a faulty pull-down field-effect transistor by this approach is even more difficult because a defective pull-down field-effect transistor may appear to be functioning properly.
The traditional approach of testing the field-effect transistors in random access memory arrays has thus exhibited serious shortcomings. Considerable time, on the order of seconds, is required to test an average sized array. Also, even after such testing, it is not always assured that all defective cells have been located.